SAF-XC886-8FFA 查看數據表（PDF） - Infineon Technologies

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SAF-XC886-8FFA

8-Bit Single-Chip Microcontroller

Infineon Technologies 

XC886/888CLM

Functional Description

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected

bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the

bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit

field PASS closes access to writing of all protected bits. Note that access is opened for

maximum 32 CCLKs if the “close access” password is not written. If “open access”

password is written again before the end of 32 CCLK cycles, there will be a recount of

32 CCLK cycles. The protected bits include the N- and K-Divider bits, NDIV and KDIV;

the Watchdog Timer enable bit, WDTEN; and the power-down and slow-down enable

bits, PD and SD.

PASSWD

Password Register

7

6

5

4

PASS

wh

Reset Value: 07H

3

2

1

0

PROTECT

_S

rh

MODE

rw

Field

MODE

PROTECT_S

PASS

Bits Type Description

[1:0] rw

Bit Protection Scheme Control bits

00 Scheme Disabled

11 Scheme Enabled (default)

Others: Scheme Enabled

These two bits cannot be written directly. To change

the value between 11B and 00B, the bit field PASS

must be written with 11000B; only then, will the

MODE[1:0] be registered.

2

rh Bit Protection Signal Status bit

This bit shows the status of the protection.

0 Software is able to write to all protected bits.

1 Software is unable to write to any protected

bits.

[7:3] wh

Password bits

The Bit Protection Scheme only recognizes three

patterns.

11000B Enables writing of the bit field MODE.

10011B Opens access to writing of all protected bits.

10101B Closes access to writing of all protected bits.

Data Sheet

Prelimary

27

V0.1, 2006-02

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