SAF7129AH 查看數據表（PDF） - NXP Semiconductors.
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SAF7129AH Datasheet PDF : 56 Pages
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Philips Semiconductors
Digital video encoder
Product specification
SAF7129AH
6 PINNING
SYMBOL PIN TYPE
DESCRIPTION
RES
1
− reserved pin; do not connect
SP
2
I test pin; connected to digital ground for normal operation
AP
3
I test pin; connected to digital ground for normal operation
LLC1
4
I line-locked clock input; this is the 27 MHz master clock
VSSD1
VDDD1
RCV1
5 supply digital ground 1
6 supply digital supply voltage 1
7 I/O raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
RCV2
8 I/O raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse
MP7
MP6
MP5
MP4
9
I double-speed 54 MHz MPEG port; it is an input for “ITU-R BT.656” style multiplexed
10
I CB-Y-CR data; data is sampled on the rising and falling clock edge; data sampled on the
11
I
rising edge is then sent to the encoding part of the device; data sampled on the falling edge
is sent to the RGB part of the device (or vice versa, depending on programming)
12 I
MP3
13 I
MP2
14 I
MP1
15 I
MP0
16 I
VDDD2
VSSD2
RTCI
17 supply digital supply voltage 2
18 supply digital ground 2
19 I real-time control input; if the LLC1 clock is provided by an SAF7113 or SAF7118, RTCI
should be connected to the RTCO pin of the respective decoder to improve the signal
quality
n.c.
20 − not connected
SA
21 I select I2C-bus address; LOW selects slave address 88H, HIGH selects slave address 8CH
DUMP2 22 O current return path 2 for DAC
RED
C
23 O analog output of RED (CR) signal
24 O analog output of chrominance (CVBS) signal
VDDA2
GREEN
25 supply analog supply voltage 2 for analog outputs
26 O analog output of GREEN (Y) signal
VBS
27 O analog output of VBS (CVBS) signal
VDDA1
BLUE
CVBS
28 supply analog supply voltage 1 for analog outputs
29 O analog output of BLUE (CB) signal
30 O analog output of CVBS (CSYNC) signal
RSET
31
DUMP1 32
O a resistor of 1 kΩ (Rout = 37 kΩ) connected to VSSA sets the full-scale DAC current
O current return path 1 for DAC
VSSA
XTALO
33 supply analog ground for the DAC reference ladder and the oscillator
34 O crystal oscillator output
XTALI
35 I crystal oscillator input; if the oscillator is not used, this pin should be connected to ground
VDDA3
XCLK
36 supply analog supply voltage 3 for the DAC reference ladder and the oscillator
37 O clock output of the crystal oscillator
2004 Mar 16
6
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