SC1211 查看數據表（PDF） - Semtech Corporation
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SC1211 Datasheet PDF : 11 Pages
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SC1211
POWER MANAGEMENT
Applications Information (Cont.)
tor. The capacitor value can be calculated based on the
total gate charge of the top FET, QTOP, and an allowed
voltage ripple on the capacitor, ∆VBST, in one PWM cycle:
CBST > QTOP/∆VBST
Typically, it is recommended to use a 1uF ceramic ca-
pacitor with 25V rating and a commonly available diode
IN4148 for the bootstrap circuit. In addition, a small re-
sistor (one ohm) has to be added in between DRN of the
SC1211 and the Phase Node. The resistor is used to
allievate the stress of the SC1211 from exposing to the
negative spike at the Phase node. A negative spike could
occur at the Phase Node during the top FET turn-off due
to parasitic inductance in the switching loop. The spike
could be minimized with a careful PCB layout. In those
applications with TO-220 package FETs, it is recom-
mended to use a clamping diode on the DRN pin to miti-
gate the impact of the excessive phase node negative
spike.
3. Locate the components of the bootstrap circuit close
to the SC1211.
SOLDERING CONSIDERATION
The exposed die pad of the SC1211 is used for ground
Solder Pad
Solder Mask
Copper
Filters for Supply Power
Vias
For VREG pin of the SC1211, it is recommended to use
a 1uF to 4.7uF, 25V rating ceramic capacitor for
decoupling.
LAYOUT GUIDELINES
The switching regulator is a high di/dt power circuit. Its
Printed Circuit Board (PCB) layout is critical. A good lay-
out can achieve an optimum circuit performance while
minimized the component stress, resulting in better sys-
tem reliability. For a multi-phase voltage regulator, the
SC1211 driver, FETs, inductor, and supply decoupling
capacitors in each phase have to be considered as a
whole during PCB layout. Refer to Semtech SC2643VX/
SC1211 EVB Layout Guideline.
return and thermal release of the driver. The pad must
be soldered to the ground plane that is further connected
to the system ground in the inner layer through multiple
vias. For better electrical and thermal performance, it is
recommended to use all copper available under the driver
as the ground plane, and place the vias as close as pos-
sible to the solder pad. Meanwhile, the vias have to be
masked out to prevent solder leakage during reflow. The
layout arrangement is detailed in the above figure, which
also can be found in the “Land Pattern – Power SOIC-8”
section.
For the SC1211 driver, the following guidelines are typi-
cally recommended during PCB layout:
1. Place the SC1211 close to the FETs for shortest gate
drive traces and ground return paths.
2. Connect bypass capacitors as close as possible to
decoupling pins (VREG and VIN) and PGND. The trace
length of the decoupling capacitor on VREG pin should
be no more than 0.2” (5mm).
2003 Semtech Corp.
10
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