SC18IS602IPW 查看數據表（PDF） - NXP Semiconductors.
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SC18IS602IPW Datasheet PDF : 25 Pages
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NXP Semiconductors
SC18IS602/602B/603
I2C-bus to SPI bridge
7.1.11 GPIO Configuration - Function ID F7h
The pins defined as GPIO may be configured by software to one of four types on a
pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only.
Two bits select the output type for each port pin.
Table 9. GPIO Configuration (F7h) bit allocation
7
6
5
4
3
SS3.1[1] SS3.0[1]
SS2.1
SS2.0
SS1.1
[1] SS3.1 and SS3.0 do not exist in the SC18IS603.
2
SS1.0
1
SS0.1
0
SS0.0
Table 10. GPIO Configuration (F7h) bit description
Bit
Symbol Description
7
SS3.1[1]
SS3[1:0] = 00: quasi-bidirectional
6
SS3.0[1]
SS3[1:0] = 01: push-pull
SS3[1:0] = 10: input-only (high-impedance)
SS3[1:0] = 11: open-drain
5
SS2.1
SS2[1:0] = 00: quasi-bidirectional
4
SS2.0
SS2[1:0] = 01: push-pull
SS2[1:0] = 10: input-only (high-impedance)
SS2[1:0] = 11: open-drain
3
SS1.1
SS1[1:0] = 00: quasi-bidirectional
2
SS1.0
SS1[1:0] = 01: push-pull
SS1[1:0] = 10: input-only (high-impedance)
SS1[1:0] = 11: open-drain
1
SS0.1
SS0[1:0] = 00: quasi-bidirectional
0
SS0.0
SS0[1:0] = 01: push-pull
SS0[1:0] = 10: input-only (high-impedance)
SS0[1:0] = 11: open-drain
[1] SS3.1 and SS3.0 do not exist in the SC18IS603.
The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by
software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and
input-only. Two configuration bits in GPIO Configuration register for each pin select the
type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression
circuit. For SC18IS603, the SS3 pin defined as GPIO is non-existent.
7.1.11.1 Quasi-bidirectional output configuration
Quasi-bidirectional outputs can be used both as an input and output without the need to
reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a large current. There are three pull-up
transistors in the quasi-bidirectional output that serve different purposes.
One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch
for the pin contains a logic 1. This very weak pull-up sources a very small current that will
pull the pin HIGH if it is left floating.
SC18IS602_602B_603_4
Product data sheet
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
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