SCC2681 查看數據表（PDF） - Philips Electronics
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SCC2681 Datasheet PDF : 29 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC2681
PIN CONFIGURATIONS
A0 1
IP3 2
40 VCC
39 IP4
A1 3
38 IP5
IP1 4
37 IP6
A2 5
36 IP2
A3 6
35 CEN
IP0 7
34 RESET
WRN 8
33 X2
RDN 9
32 X1/CLK
RXDB 10
31 RXDA
DIP
TXDB 11
30 TXDA
OP1 12
29 OP0
OP3 13
28 OP2
OP5 14
27 OP4
OP7 15
D1 16
26 OP6
25 D0
D3 17
24 D2
D5 18
23 D4
D7 19
22 D6
GND 20
21 INTRN
A0 1
A1 2
A2 3
28 VCC
27 IP2
26 CEN
A3 4
25 RESET
WRN 5
24 X2
RDN 6
23 X1/CLK
RXDB 7
TXDB 8
22 RXDA
DIP
21 TXDA
OP1 9
20 OP0
D1 10
19 D0
D3 11
18 D2
D5 12
17 D4
D7 13
16 D6
GND 14
15 INTRN
INDEX
CORNER
6
7
1
40
39
PLCC
17
18
TOP VIEW
29
28
PIN/FUNCTION
1 NC
2 A0
3 IP3
4 A1
5 IP1
6 A2
7 A3
8 IP0
9 WRN
10 RDN
11 RXDB
12 NC
13 TXDB
14 OP1
15 OP3
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 GND
PIN/FUNCTION
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
31 OP2
32 OP0
33 TXDA
34 NC
35 RXDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
41 IP6
42 IP5
43 IP4
44 VCC
SD00723
PIN DESCRIPTION
PIN
SYMBOL
PLCC44 DIP40
D0–D7
28, 18,
27, 19,
26, 20,
25, 21
25, 16,
24, 17,
23, 18,
22, 19
CEN
39
35
WRN
RDN
9
8
10
9
A0–A3
RESET
2, 4, 6, 7
38
1, 3, 5,
6
34
INTRN
24
21
X1/CLK
36
32
Figure 1. Pin configurations
DIP28
19, 10,
18, 11,
17, 12,
16, 13
26
5
6
1–4
25
15
23
TYPE
NAME AND FUNCTION
I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status
between the DUART and the CPU. D0 is the least significant bit.
I Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU
and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3
inputs. When HIGH, places the D0-D7 lines in the 3-State condition.
I Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the signal.
I Read Strobe: When LOW and CEN is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RDN.
I Address Inputs: Select the DUART internal registers and ports for read/write
operations.
I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the
inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test
modes, sets MR pointer to MR1.
O Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or
more of the eight maskable interrupting conditions are true.
I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the
appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal
connections see Figure 7, Clock Timing.
2004 Apr 06
3
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