AKD4363 查看數據表（PDF） - Asahi Kasei Microdevices

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AKD4363

96kHz 24Bit ∆Σ DAC with PLL

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4363]

Parameter

Symbol

min

typ

Control Interface Timing (3-wire Serial mode):

CCLK Period

tCCK

200

CCLK Pulse Width Low

tCCKL

80

Pulse Width High

tCCKH

80

CDTI Setup Time

tCDS

40

CDTI Hold Time

tCDH

40

CSN “H” Time

tCSW

150

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

Control Interface Timing (I2C Bus mode):

tCSS

50

tCSH

50

SCL Clock Frequency

fSCL

-

Bus Free Time Between Transmissions

tBUF

4.7

Start Condition Hold Time (prior to first clock pulse) tHD:STA 4.0

Clock Low Time

tLOW

4.7

Clock High Time

tHIGH

4.0

Setup Time for Repeated Start Condition

tSU:STA

4.7

SDA Hold Time from SCL Falling

(Note 12) tHD:DAT

0

SDA Setup Time from SCL Rising

tSU:DAT 0.25

Rise Time of Both SDA and SCL Lines

tR

-

Fall Time of Both SDA and SCL Lines

tF

-

Setup Time for Stop Condition

tSU:STO

4.0

Pulse Width of Spike Noise suppressed by Input Filter tSP

0

Note:12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

max Units

ns

ns

ns

ns

ns

ns

ns

ns

100 kHz

-

µs

-

µs

-

µs

-

µs

-

µs

-

µs

-

µs

1.0

µs

0.3

µs

-

µs

50

ns

MS0015-E-01

- 11 -

2000/07

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