SI4012 查看數據表（PDF） - Silicon Laboratories
零件编号
产品描述 (功能)
比赛名单
SI4012 Datasheet PDF : 50 Pages
| |||
Si4012
4. Host MCU Interface
4.1. SMBus Interface
The SMBus interface is implemented as a bidirectional 2-wire interface (SCL, SDA) with the host configured as
master and the Si4012 configured as slave. Both standard (100 kbps) and fast (400 kbps) modes are supported
with 7-bit addressing. The default device address is 1110000x, where x is the R/W bit.
4.1.1. Design Recommendation
In designs with multiple SMBus devices, it is recommended to use separate SMBus buses where possible since all
attached SMBus devices will wake on bus traffic to confirm address. This process can lead to better battery life
compared to systems with single-bus designs.
4.2. SMBus Flow Control
The SCL and SDA pins are configured as open drain requiring external pull-up resistors. Flow control is
implemented using the open drain configuration as shown below.
Figure 2. WRITE Operation from Master to Slave
The data (SDA) pin never changes when SCL = 1 during bit data transfers. If it changes, it indicates a START or
STOP condition generated by the master/host. After the START condition, a 7-bit address is sent to the
Si4012/slave by the host/master, followed by a single bit determining what is going to drive SDA (i.e., a write or
read operation). For a WRITE operation, the master drives the following SDA bits, and the slave sends ACK/NAK
bits. For a READ operation, the slave drives the data bits, and the master responds with ACK/NACK.
Figure 2 shows a write operation from MASTER to SLAVE. Shortly after the R/W bit is received, the SLAVE device
holds the SCL line low (blue line), thus stalling the master. The master will detect when SCL is released by the
slave and will clock in the ACK/NACK bit from the slave (ACK shown above). By this, the slave (Si4012) can
service each incoming byte and manage flow control to the host.
4.3. Host Interrupts
An nIRQ line from the Si4012 to the host is used to issue interrupts to the host. The host can then read the interrupt
status and clear interrupts from the Si4012 via the SMBus interface.
10
Rev 1.1
Share Link: 