SL74HC74 查看數據表（PDF） - System Logic Semiconductor
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SL74HC74 Datasheet PDF : 5 Pages
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SL74HC74
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay, Set or Reset to Q
or Q (Figures 2 and 4)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
CIN
Maximum Input Capacitance
VCC
Guaranteed Limit
V 25 °C ≤85°C ≤125°C Unit
to
-55°C
2.0 6.0
4.8
4.0 MHz
4.5
30
24
20
6.0
35
28
24
2.0 100
125
150
ns
4.5
20
25
30
6.0
17
21
26
2.0 105
130
160
ns
4.5
21
26
32
6.0
18
22
27
2.0
75
95
110
ns
4.5
15
19
22
6.0
13
16
19
-
10
10
10
pF
Power Dissipation Capacitance (Per Flip-Flop)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
39
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V 25 °C to-55°C ≤85°C ≤125°C Unit
tsu
Minimum Setup Time, Data to Clock
2.0
80
(Figure 3)
4.5
16
6.0
14
100
120
ns
20
24
17
20
th
Minimum Hold Time, Clock to Data
2.0
3.0
(Figure 3)
4.5
3.0
6.0
3.0
3.0
3.0
ns
3.0
3.0
3.0
3.0
trec
Minimum Recovery Time, Set or Reset 2.0
8.0
Inactive to Clock (Figure 2)
4.5
8.0
6.0
8.0
8.0
8.0
ns
8.0
8.0
8.0
8.0
tw
Minimum Pulse Width, Clock (Figure 2.0
60
1)
4.5
12
6.0
10
75
90
ns
15
18
13
15
tw
Minimum Pulse Width, Set or Reset
2.0
60
(Figure 2)
4.5
12
6.0
10
75
90
ns
15
18
13
15
tr, tf Maximum Input Rise and Fall Times
2.0
1000
(Figure 1)
4.5
500
6.0
400
1000
1000
ns
500
500
400
400
SLS
System Logic
Semiconductor
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