AD7628KP 查看數據表（PDF） - Analog Devices

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AD7628KP

CMOS Dual 8-Bit Buffered Multiplying DAC

Analog Devices 

MICROPROCESSOR INTERFACE

AD7628

Figure 11. AD7628 Dual DAC to 6800 CPU Interface

PROGRAMMABLE WINDOW COMPARATOR

Figure 12. AD7628 Dual DAC to 8085 CPU Interface

In the circuit of Figure 13, the AD7628 is used to implement a

programmable window comparator. DACs A and B are loaded

with the required upper and lower voltage limits for the test,

respectively. If the test input is not within the programmed lim-

its, the pass/fail output will indicate a fail (logic zero).

Figure 13. Digitally Programmable Window Comparator

(Upper and Lower Limit Detector)

PROGRAMMABLE STATE VARIABLE FILTER

CIRCUIT EQUATIONS

C1 = C2, R1 = R2, R4 = R5

1

fC = 2π R1 C1

Q=

R3 . RF

R4 RFBB1

AO = –

RF

RS

NOTE

DAC equivalent resistance equals

( ) 256 × DAC Ladder resistance

DAC Digital Code

Figure 14. Digitally Controlled State Variable Filter

In this state, variable or universal filter configuration (Figure

14) for DACs A1 and B1 control the gain and Q of the filter

characteristic, while DACs A2 and B2 control the cutoff fre-

quency, fC. DACs A2 and B2 must track accurately for the simple

expression for fC to hold. This is readily accomplished by the

AD7628. Op amps are 2 × AD644. C3 compensates for the

effects of op amp gain-bandwidth limitations.

The filter provides low pass, high pass and band pass outputs

and is ideally suited for applications where microprocessor con-

trol of filter parameters is required, e.g., equalizer, tone con-

trols, etc.

Programmable range for component values shown is fC = 0 kHz

to 15 kHz and Q = 0.3 to 4.5.

REV. A

–7–

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