UT61L256CJC-10 查看數據表（PDF） - Utron Technology Inc

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UT61L256CJC-10

32K X 8 BIT HIGH SPEED CMOS SRAM

Utron Technology Inc 



UTRON

Rev. 1.1

UT61L256C

32K X 8 BIT HIGH SPEED CMOS SRAM

WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)

tWC

Address

tAW

CE

tCW

tAS

tWP

tWR

WE

DOUT

tWHZ

High-Z

tOW

(4)

(4)

tDW

tDH

DIN

WRITE CYCLE 2 ( CE Controlled) (1,2,5)

Data Valid

tWC

Address

tAW

CE

tAS

tCW

tWR

tWP

WE

DOUT

tWHZ

(4)

High-Z

tDW

tDH

DIN

Data Valid

Notes :

1. WE or CE must be HIGH during all address transitions.

2. A write occurs during the overlap of a low CE and a low WE .

3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to

turn off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high

impedance state.

6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ± 500mV from steady state.

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80058

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

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