UT61L5128 查看數據表（PDF） - Utron Technology Inc
零件编号
产品描述 (功能)
比赛名单
UT61L5128 Datasheet PDF : 8 Pages
| |||
Rev. 1.0
UTRON
UT61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
DOUT
tAA
tOH
tOH
Data Valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
Address
CE
tRC
tAA
tACE
OE
DOUT
tCLZ
High-z
tOE
tOLZ
tCHZ
tOHZ
tOH
Data valid
High-Z
Notes :
1. WE is HIGH for read cycle.
2. Device is continuously selected CE =VIL.
3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80061
Share Link: 