UT62L1024PC-55LE(Rev1_1) 查看數據表（PDF） - Utron Technology Inc
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UT62L1024PC-55LE Datasheet PDF : 12 Pages
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UTRON
Rev. 1.1
UT62L1024(E)
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
t WC
Address
CE1
CE2
WE
t AS
t AW
t CW1
t CW2
t WP
t WR
Dout
Din
t WHZ
(4)
High-Z
t DW
t OW
(4)
t DH
Data Valid
WRITE CYCLE 2 ( CE1 and CE2 Controlled) (1,2,5)
t WC
Address
CE1
t AS
CE2
t AW
t CW1
t CW2
t WR
WE
Dout
Din
t WHZ
t WP
High-Z
t DW
t DH
Data Valid
Notes :
1. WE or CE1 must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low CE1 , a high CE2 and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn
off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
4. If the CE1 LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state.
6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80053
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