UT62L1024LC-55LL(Rev1_7) 查看數據表（PDF） - Utron Technology Inc

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UT62L1024LC-55LL
(Rev.:Rev1_7)

128K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Rev. 1.7

UT62L1024

128K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (Ta = 0℃ to +70℃)

PARAMETER

Vcc for Data Retention

Data Retention Current

SYMBOL TEST CONDITION

VDR

CE 1 ≧ VCC-0.2V or

CE2 ≤ 0.2V

IDR

Vcc=2V

CE 1 ≧ VCC-0.2V or

CE2 ≤ 0.2V

Chip Disable to Data

Retention Time

tCDR See Data Retention

Waveforms (below)

Recovery Time

tR

tRC* = Read Cycle Time

*Those parameters are for reference only under 50℃

MIN. TYP. MAX. UNIT

2.0 - 3.3 V

-L

-

1

40 µA

20*

- LL -

20 µA

0.5

5*

0-

-

ns

tRC* -

-

ns

DATA RETENTION WAVEFORM

VCC

CE1

VSS

CE2

2.7V

tCDR

VIH

VIL

Date Retention Mode

VDR ≧ 2.0V

CE1 ≧ VCC -0.2V

CE2 ≤ 0.2V

2.7V

tR

VIH

VIL

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

7

P80033

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