PM7328-BI 查看數據表（PDF） - PMC-Sierra

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PM7328-BI

ATM LAYER SOLUTION

PMC-Sierra 

STANDARD PRODUCT

DATASHEET

PMC-2010142

ISSUE 2

PM7328 S/UNI-ATLAS-1K800

ATM LAYER SOLUTION

8.11.3 CONTINUOUSLY VIOLATING MODE ........................... 116

8.11.4 S/UNI-ATLAS-1K800 POLICING CONFIGURATION..... 117

8.12 CELL COUNTING ..................................................................... 117

8.13 OPERATIONS, ADMINISTRATION AND MAINTENANCE (OAM)

CELL SERVICING..................................................................... 121

8.14 FAULT MANAGEMENT CELLS ................................................ 124

8.15 LOOPBACK CELLS .................................................................. 126

8.16 ACTIVATION/DEACTIVATION CELLS..................................... 126

8.17 SYSTEM MANAGEMENT CELLS............................................. 126

8.18 F4 TO F5 OAM PROCESSING ................................................. 127

8.19 F5 TO F4 OAM PROCESSING ................................................. 137

8.20 RESOURCE MANAGEMENT CELLS ....................................... 144

8.21 S/UNI-ATLAS-1K800 BACKGROUND PROCESSES............... 144

8.22 INGRESS BACKWARD OAM CELL INTERFACE .................... 146

8.23 EGRESS BACKWARD OAM CELL INTERFACE ..................... 147

8.24 JTAG TEST ACCESS PORT .................................................... 147

8.25 MICROPROCESSOR INTERFACE .......................................... 147

8.26 EXTERNAL SRAM ACCESS .................................................... 148

8.27 WRITING CELLS ...................................................................... 148

8.28 READING CELLS...................................................................... 152

8.29 S/UNI-ATLAS-1K800 DLL CLOCK OPERATION...................... 155

9 NORMAL MODE REGISTER MEMORY MAP..................................... 156

9.1 NORMAL MODE REGISTER DESCRIPTION .......................... 167

10 TEST FEATURES DESCRIPTION ...................................................... 436

10.1 TEST MODE 0 DETAILS .......................................................... 439

10.2 JTAG TEST PORT .................................................................... 439

11 OPERATION........................................................................................ 446

11.1 SCI-PHY EXTENDED CELL FORMAT ..................................... 446

11.2 SYNCHRONOUS STATIC RAMS ............................................. 448

11.2.1 INGRESS VC-TABLE SRAM.......................................... 448

PROPRIETARY AND CONFIDENTIAL

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