SM5885CS 查看數據表（PDF） - Nippon Precision Circuits

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SM5885CS

Audio 3rd-order Σ∆ D/A Converter

Nippon Precision Circuits  

SM588× series

FUNCTIONAL DESCRIPTION

System Clock (CLK)

The system clock CLK frequency varies with device within the series as shown below, where fs is the input

frequency on LRCI.

Note that the input clock accuracy and signal-to-noise ratio greatly influence the AC analog characteristics.

The D/A converter operates at the speed shown in the following table.

Table 1. System clock

Device

A version

B, C version

Master clock

384fs

256/512fs

DAC oversampling

operation

48fs

32fs

System Reset

The SM588× series devices incorporate a built-in power-ON reset circuit for system reset.

When power is applied, the internal arithmetic operation and output timing counter are reset, and then reset

again and timing synchronized to the external input on the next LRCI rising edge. After system reset, the out-

puts are muted until the 9th rising of LRCI when output muting is released.

When the timing is reset, the PWM outputs may generate an output noise. An external muting circuit may be

required to prevent this output noise.

VDD

LRCI

Internal

Reset

LO

RO

1

2

3

9 10

Output Muted

Figure 1. System reset timing

NIPPON PRECISION CIRCUITS—12

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