YMF753 查看數據表（PDF） - Yamaha Corporation
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YMF753 Datasheet PDF : 26 Pages
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YMF753
28h : Extended Audio ID (Read Only, Default: xxx4h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ID1 ID0 -
-
REV1-0 AMAP LDAC SDAC CDAC -
-
- SPDIF -
-
ID1,ID0.........These bits indicate CODEC ID. The states are determined by setting both No.46 and 45 pins.
When MSEL is high, they are fixed to “Primary ID00”.
ID1# (No.46)
Pin Status Logic Value
ID0# (No.45)
Pin Status Logic Value
CODEC ID
Configuration
OPEN (“H”)
“0”
OPEN (“H”)
“0”
Primary ID00
OPEN (“H”)
“0”
GND (“L”)
“1”
Secondary ID01
GND (“L”)
“1”
OPEN (“H”)
“0”
Secondary ID10
GND (“L”)
“1”
GND (“L”)
“1”
Secondary ID11
REV1-0.........These bits are hardwired to “01b”, which indicates AC’97 Revision 2.2 Compliant.
AMAP...........This bit is hardwired to “1”. It indicates that the PCM DAC uses data of the standard slot into
twelve slots, as the following table.
CODEC
ID
Slot Number
PCM Left DAC PCM Right DAC
00
Slot 3
Slot 4
Original definition (master)
01
Slot 3
Slot 4
Original definition (docking)
10
Slot 7
Slot 8
Left / Right surround channels
11
Slot 6
Slot 9
Center / LFE channels
LDAC ...........When PCM DAC uses the LFE channel, this bit is set to “1”.
SDAC ...........When PCM DAC uses the surround channels, this bit is set to “1”.
CDAC ...........When PCM DAC uses the center channel, this bit is set to “1”.
SPDIF ...........This bit is hardwired to “1”, which indicates that SPDIF output is compliant with AC’97
Revision 2.2.
2Ah : Ext Audio Stat/Ctrl (Read/Write, Default: 0400h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
-
- SPCV -
-
-
-
SPSA1-0
- SPDIF -
-
SPCV ............This bit is hardwired to “1”, which indicates that SPDIF output configuration is valid.
SPSA1-0 .......These bits select DIT output slot.
SPSA1
SPSA0 L-ch Slot Number R-ch Slot Number
0
0
Slot 3
Slot 4
0
1
Slot 7
Slot 8
1
0
Slot 6
Slot 9
1
1
Slot 10
Slot 11
SPDIF ...........This bit selects whether the SPDIF signal is output from DIT or not.
“0” : DIT is power down state, and outputs low level.
“1” : SPDIF signal is output from DIT.
12
March 6, 2001
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