AK4544A 查看數據表（PDF） - Asahi Kasei Microdevices

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AK4544A

AC’ 97™ Multimedia Audio CODEC with SRC

Asahi Kasei Microdevices 

[ASAHI KASEI]

[AK4544A]

nWarm Reset

The AK4544A initiates warm reset process by receiving a single pulse on the sync. The AK4544A clears PR4 bit and

PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0∼PR3 or PR6,7 bits in

Powerdown Control Register. Note that SYNC signal should synchronize with BIT_CLK after AK4544A starts to

output BIT_CLK clock. And if an external clock is used, external clocks should be supplied before issuing a sync

pulse for warm reset.

ADC and DAC require 1028TS for the initialization.

SYNC

Tsync_high

Tsync2clk

VIH

BIT_CLK

Please refer to the appendix on the warm reset when the AK4544A is used under the multiple codec configuration.

nBIT_CLK Timing

Tclk_high

BIT_CLK

Tclk_low

50%

nSYNC Timing

SYNC

Tsync_high

Tsync_low

Tsync_period

nSetup and Hold Timing

BIT_CLK

Tdelay

Tsetup

SDATA_IN

SDATA_OUT

SYNC

Thold

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

<MS0026-E-00>

-9-

2000/04

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