SP3249 查看數據表（PDF） - Signal Processing Technologies

零件编号

产品描述 (功能)

比赛名单

SP3249

Intelligent +3.0V to +5.5V RS-232 Transceivers

Signal Processing Technologies 

— VDD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C1 produces –VCC in the negative

terminal of C1, which

side of capacitor C2.

is applied to the

Since C2+ is at

negative

VCC, the

voltage potential across C2 is 2 times VCC.

Phase 4 (Figure 15)

— VDD transfer — The fourth phase of the clock

connects the negative terminal of C2 to GND,

and transfers this positive generated voltage

across C2 to C4, the VDD storage capacitor. This

voltage is regulated to +5.5V. At this voltage,

the internal oscillator is disabled. Simultaneous

with the transfer of the voltage to C4, the

positive side of capacitor C1 is switched to VCC

and the negative side is connected to GND,

allowing the charge pump cycle to begin again.

The charge pump cycle will continue as long as

the operational conditions for the internal

oscillator are present.

Since both V+ and V– are separately generated

from VCC, in a no–load condition V+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically

operates at 500kHz. The external capacitors can

be as low as 0.1µF with a 16V breakdown

voltage rating.

Figure 10. Charge Pump — Phase 1

VCC = +5V

+

C1 –

–5V

+5V

+

C2 –

–5V

VCC = +5V

+

C1 –

Figure 11. Charge Pump — Phase 2

+

C2 –

–10V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

a) C2+

1

2

2

[

T

T

]

+6V

0V

0V

b) C2-

T

-6V

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V

Figure 12. Charge Pump Waveforms

Rev.4/08/02

SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers

8

© Copyright 2002 Sipex Corporation

Share Link: