CXD2053AM 查看數據表（PDF） - Sony Semiconductor
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CXD2053AM Datasheet PDF : 14 Pages
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CXD2053AM/AS
3. Description of EDTV-II ID
As shown in the table below, EDTV-II ID consists of 27-bit data. On an NTSC video signal, this information is
carried on lines 22 and 285 of the vertical blanking interval.
Bit
No.
Description
1 Reference signal
2 Reference signal
3 Letter-box
4 Parity of bits 3 and 5
5 Undefined
6 Field No.
7 Multiphase
8 VT
9 VH
10 HH
11 HH precombing
12 Broadcasting station operation bit
13 Broadcasting station operation bit
14 Broadcasting station operation bit
0
—
0
Full line
0
0
1
A
No
No
No
No
Bit
1
No.
Description
01
1
15 Undefined
——
—
16 Undefined
——
Letter-box 17 Undefined
——
1
18 Error correction signal
—
19 Error correction signal
2
20 Error correction signal
B
21 Error correction signal
Yes
22 Error correction signal
Yes
23 Error correction signal
Yes
24 0
0—
Yes
25 Confirmation sine wave
26 Confirmation sine wave
27 Confirmation sine wave
Table 2. Description of EDTV-II ID (discrimination control signal) signal
Of the 27 bits noted above, the CXD2053AM/AS outputs only bits 3 and 5. These 2 bits are obtained by the I2C
bus during bus mode. Also, bit 3 only is output directly to the OED (Pin 28) regardless of bus or bus-free mode.
Since the CXD2053AM/AS does not perform decode processing for bits 6 to 23, this results in simple
identification which does not use the error correction signals.
4. Clock
The CXD2053AM/AS requires a 4fsc clock (14.318MHz). Connect XI (Pin 22) and XO (Pin 21) when using a
crystal oscillator.
When inputting the clock from an external source, input to XI (Pin 22).
Clock is 14.318MHz regardless of switching auto wide 525/60 (NTSC) or 625/50 (PAL, SECAM).
5. Settings and data input/output
The CXD2053AM/AS settings and data input/output can be performed by direct setting by pins or with the I2C
bus interface.
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