SP488ACP 查看數據表（PDF） - Signal Processing Technologies

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SP488ACP

High Speed Quad RS-485/RS-422 Line Receivers

Signal Processing Technologies 

A

DI DRIVER

B

1/4 SP486

50pF EN

54Ω

RCVR

50pF

EN

1/4 SP488

ROn

CL

Figure 3. Timing Test Circuit

RCVR

CL

S1

1kΩ

S2

1kΩ

VCC

Figure 4. Enable/Disable Timing Test Circuit

SP489A PINOUT

Pin 1 — RI1B — Receiver 1 input B.

Pin 2 — RI1A — Receiver 1 input A.

Pin 3 — RO1 — Receiver 1 Output — If Re-

ceiver 1 output is enabled, if RI1A > RI1B by

200mV, Receiver output is high. If Receiver 1

output is enabled, and if RI A< RI B by 200mV,

1

1

Receiver 1 output is low.

Pin 4 — EN1/EN2 — Receiver 1 and 2 Output

Enable. Please refer to SP489A Truth Table (2).

Pin 5 — RO2 — Receiver 2 Output — If Re-

ceiver 2 output is enabled, if RI2A > RI2B by

200mV, Receiver 2 output is high. If Receiver 2

output is enabled, and if RI2A < RI2B by

200mV, Receiver 2 output is low.

Pin 6 — RI A — Receiver 2 input A.

2

Pin 7 — RI2B — Receiver 2 input B.

Pin 8 — GND — Digital Ground.

Pin 9 — RI3B — Receiver 3 input B.

Pin 10 — RI3A — Receiver 3 input A.

Pin 11 — RO — Receiver 3 Output — If

3

Receiver 3 output is enabled, if RI A > RI B by

3

3

200mV, Receiver 3 output is high. If Receiver 3

output is enabled, and if RI3A < RI3B by

200mV, Receiver 3 output is low.

Pin 12 — EN3/EN4 — Receiver 3 and 4 Output

Enable. Please refer to SP489A Truth Table (2).

Pin 13 — RO4 — Receiver 4 Output — If

Receiver 4 output is enabled, if RI4A > RI4B by

200mV, Receiver 4 output is high. If Receiver 4

output is enabled, and if RI A < RI B by

4

4

200mV, Receiver 4 output is low.

Pin 14 — RI A — Receiver 4 input A.

4

Pin 15 — RI B — Receiver 4 input B.

4

Pin 16 — Supply Voltage VCC — 4.75V ≤ VCC ≤

5.25V.

SP488A/489ADS/07

SP488A/489A High Speed Quad RS-485/RS-422 Line Receivers

5

© Copyright 2000 Sipex Corporation

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