SPLC782A 查看數據表（PDF） - Unspecified

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SPLC782A

16COM/80SEG Controller/Driver

Unspecified 

SPLC782A

5.3. Instruction Table

Instruction

Instruction Code

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

Max. Execution time

(Temp = -20℃ ~ +75℃)

Write "20H" to DDRAM

Clear Display

0 0 0 0 0 0 0 0 0 1 and set DDRAM address

4.1ms

to "00H" from AC

Set DDRAM address to

"00H" from AC and

Return Home

tial Entry Mode

n Set

fide Display ON/

e OFF Control

on Us Cursor or

C R Display Shift

nplus MINE Function Set

Su RT Set CGRAM

A Address

Set DDRAM

P Address

For Read Busy Flag

return cursor to its

000000001 -

original position if shifted.

The contents of DDRAM

are not changed.

Assign cursor moving

0 0 0 0 0 0 0 1 I/D S direction and enable the

shift of entire display

Set

display

(D),

cursor(C), and blinking of

0 0 0 0 0 0 1DCB

cursor(B) on/off control

bit.

Set cursor moving and

display shift control bit,

0 0 0 0 0 1 S/C R/L - - and the direction, without

changing of DDRAM

data.

Set interface data length

(DL: 8-bit/4-bit), numbers

of display line (N:

0 0 0 0 1 DL N F - -

2-line/1-line) and, display

font type (F:5x10

dots/5x8 dots)

Set CGRAM address in

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

address counter.

Set DDRAM address in

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

address counter

Whether during internal

operation or not can be

known by reading BF.

and Address

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

The contents of address

Counter

counter can also be

4.1ms

Only 100s

100s

100s

100s

100s

100s

0s

read.

Write Data to

RAM

Write data into internal

1 0 D7 D6 D5 D4 D3 D2 D1 D0

RAM (DDRAM/CGRAM).

100s

Read Data from

RAM

Read data from internal

1 1 D7 D6 D5 D4 D3 D2 D1 D0

RAM (DDRAM/CGRAM).

100s

Note: “-“ don’t care

Figure 5-16: Instruction Table

© Sunplus Technology Co., Ltd.

8

Proprietary & Confidential

FEB. 15, 2005

Version: 1.7

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