Figure 1A – Timing Diagram 1
1
ANALOG IN
CLOCK IN
SAMPLING
CLOCK
(Internal)
DATA OUTPUT
DATA VALID
3
5
9
7
INVALID
1
1
13
17
15
VALID
1 23
Figure 1B – Timing Diagram 2
CLOCK IN
tCLK
tC
tCH
tCL
DATA
OUTPUT
Data Ø
tOD
DATA
VALID
tS
Data 1
tS
tCH
Data 2
tCL
Data 3
SPT7938
4
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