MX614P 查看數據表（PDF） - MX-COM Inc
零件编号
产品描述 (功能)
比赛名单
MX614P Datasheet PDF : 19 Pages
| |||
Bell 202 Compatible Modem
10
MX614 PRELIMINARY INFORMATION
The only restrictions on the timing of the CLK waveform are those shown in Figure 7 and the need to
complete the transfer of all nine bits into the µC within the time of a complete character at 1200bps. See
Section 6.2 for Timing specifications.
FSK Demod output :
Received Character 'n'
9 Bits of data START 1
2
3
4
5
6
7
8
9 STOP
RDY output :
RXCK input :
RXD output :
1
9
Retimed data bits from
received character 'n'
RDY
RXCK
tD
RXD
tD
tcLO
tcHI
tD
Data Bit 1
Data Bit 2
tD = Internal MX614 delay, tcHI = CLK high time, tcLO = CLK low time
Figure 7: FSK Operation with Rx Data Retiming
Note that, if enabled, the Data Retiming block may interpret speech or other signals as random characters.
If the Data Retiming facility is not required, the CLK input to the MX614 should be kept high at all times. The
asynchronous data from the FSK Demodulator will then be connected directly to the RXD output pin, and the
RDY output will not be activated by the FSK signal. This case is illustrated by the example in Figure 8.
FSK Demod output :
RXD output :
Received Character 'n'
START 1
2
3
4
5
6
7
8 STOP
START 1
2
3
4
5
6
7
8 STOP
Figure 8: FSK Operation without Rx Data Retiming (CLK always high)
4.9 Tx Data Retiming
The Data Retiming block, when enabled in 1200bps transmit mode, requires the controlling µC to load one bit
at a time into the device by a pulse applied to the CLK input. The timing of this pulse is not critical and it may
easily be generated by a simple software loop. This facility removes the need for a UART in the µC without
incurring an excessive software overhead. Note: Tx Data Retiming is not supported for data rates
exceeding 1212bps.
The Tx re-timing circuit consists of two 1-bit registers in series, the input of the first is connected to the TXD
pin and the output of the second feeds the FSK modulator. The second register is clocked by an internally
generated 1200Hz signal and when this occurs the CLK input is sampled. If the CLK input is high the TXD
pin directly controls the FSK modulator, if the CLK input is low the FSK modulator is controlled by the output
of the second register and the RDY pin is pulled low. The RDY output is reset by a high level on the CLK
input pin. A low to high change on the CLK input pin will latch the data from the TXD input pin into the first
register ready for transfer to the second register when the internal 1200Hz signal next occurs.
So to use the retiming option the CLK input should be held low until the RDY output is pulled low. When the
RDY pin goes low the next data bit should be applied at the TXD input and the CLK input pulled high and then
low within the time limits set out in Figure 9. See Section 6.2 for Timing specifications.
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
All Trademarks and Service Marks are held by their respective companies.
Share Link: 