CMX644A 查看數據表（PDF） - MX-COM Inc

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CMX644A

Bell 212A and V.22 Modem with Call Progress and DTMF

MX-COM Inc  

Bell 212A / V.22 Modem with Call Progress and DTMF

9

CMX644A Preliminary Information

Bit 3 (RX DATA READY) of the FLAGS Register will be set to ‘1’ every time a new received value is loaded

into the RX DATA BYTE Register. If the previous contents of the RX DATA BYTE Register had not been read

out over the ‘C-BUS’ before the new value is loaded from the UART then bit 4 (RX DATA OVERFLOW) of the

FLAGS Register will also be set to ‘1’.

Rx DATA PSK signal:

Start D0 D1 D2 D3 D4 D5 D6 D7 P'ty Stop Start D0

RX DATA Register read:

tRDY

RX DATA READY flag bit:

RX DATA OVERFLOW flag bit:

Figure 7: Receive UART Function (Async)

The C-BUS serial clock should be fast enough to ensure that an RX DATA READY interrupt is serviced

completely within a time which is less than 8-bit times at 1200 baud, i.e. less than 6.67ms.

4.3 Software Description

4.3.1 Write-only ‘C-BUS’ Registers

REGISTER

NAME

GENERAL

RESET

SET-UP

TX

TONES

GAIN

BLOCKS

TX DATA

BYTE

UART

MODE

TX PSK

MODE

RX PSK

MODE

IRQ

MASK BITS

HEX

ADDRESS/

COMMAND

$01

$E0

$E1

$E2

$E3

$E4

$E7

$E8

$EE

BIT 7

(D7)

BIT 6

(D6)

BIT 5

(D5)

BIT 4

(D4)

BIT 3

(D3)

N/A

0

TONE

SEL

TXGAIN

TG3

D7

0

0

0

RX

PARITY

N/A

N/A

N/A

RELAY

DRIVE

DETECT

DET1

DETECT

DET0

TONE /

NOTONE

TXGAIN

TG2

DTMF /

MODEM

TONES

TXGAIN

TG1

DTMF /

SNGL

TXGAIN

TG0

D6

D5

D4

0

SYNC/

ASYNC

STOP

BITS

B

TX-

ENAB

SCRAMB SCRAMB

UNLOCK ENABLE

CPBW

SELECT

RING

DETECT

DE-

SCRAMB

UNLOCK

DETECT

DE-

SCRAMB

ENABLE

RX DATA

OVER-

FLOW

N/A

LOOP-

BACK:

L1

D3

RXGAIN

RG3

D3

STOP

BITS

A

EQUAL

ET1

EQUAL

ER1

RX

DATA

READY

Table 3: Write only 'C-BUS' Register

BIT 2

(D2)

N/A

LOOP-

BACK:

L0

D2

RXGAIN

RG2

D2

PARITY

ENABLE

EQUAL

ET0

EQUAL

ER0

TX DATA

UNDER-

FLOW

BIT 1

(D1)

N/A

XTAL

FRQ:

X1

D1

RXGAIN

RG1

D1

PARITY

ODD/

EVEN

ENABLE

ENABLE

TX

DATA

READY

BIT 0

(D0)

N/A

XTAL

FRQ:

X0

D0

RXGAIN

RG0

D0

DATA

BITS

8/7

HI / LO

BAND

HI / LO

BAND

UN-

SCRAM

MARK

4.3.2 Write-only Register Descriptions

4.3.2.1 GENERAL RESET ($01)

The reset command has no data attached to it. Application of the GENERAL RESET sets all write-only

register bits to ‘0’.

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. # 20480197.006

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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