IDT723612L15PF(1997) 查看數據表（PDF） - Integrated Device Technology

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IDT723612L15PF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

CLKA

CSA

LOW

tCLK

tCLKH tCLKL

COMMERCIAL TEMPERATURE RANGE

WRA

MBA

ENA

HIGH tENS3

tENS2

tENH3

tENH2

FFA HIGH tDS

tDH

A0 - A35

CLKB

EFB

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

FIFO1 Empty

2

tREF

tREF

CSB

W/RB

LOW

LOW

MBB LOW

ENB

B0 -B35

tENS2

tENH2

tA

W1

3136 drw 09

Note:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the

next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the

transition of EFB HIGH may occur one CLKB cycle later than shown.

Figure 6. EFB Flag Timing and First Data Read when FIFO1 is Empty

17

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