IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
Symbol
fS
tCLK
tCLKH
tCLKL
tDS
tENS1
tENS2
tENS3
tPGS
tRSTS
tFSS
tDH
tENH1
tENH2
tENH3
tPGH
tRSTH
tFSH
tSKEW1(4)
tSKEW2(4)
Parameter
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA and CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time, CSA, W/RA before CLKA↑; CSB, W/RB before CLKB↑
Setup Time, ENA, before CLKA↑; ENB before CLKB↑
Setup Time, MBA before CLKA↑: MBB before CLKB↑
Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB
before CLKB↑(2 )
Setup Time, RST LOW before CLKA↑ or CLKB↑(3)
Setup Time, FS0/FS1 before RST HIGH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA W/RA after CLKA↑; CSB, W/RB after CLKB↑
Hold Time, ENA, after CLKA↑; ENB after CLKB↑
Hold Time, MBA after CLKA↑; MBB after CLKB↑
Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB
after CLKB↑(2 )
Hold Time, RST LOW after CLKA↑ or CLKB↑(3)
Hold Time, FS0 and FS1 after RST HIGH
Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB
Skew Time, between CLKA↑ and CLKB↑ For AEA, AEB, AFA, and AFB
Commercial
IDT723612L15
Min. Max.
–
66.7
15
–
6
–
6
–
4
–
6
–
4
–
4
–
4
–
Com’l & Ind’l(1)
IDT723612L20
Min. Max. Unit
–
50 MHz
20
–
ns
8
–
ns
8
–
ns
5
–
ns
6
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
6
–
ns
5
–
6
–
ns
2.5
–
2.5
–
ns
2
–
2
–
ns
2.5
–
2.5
–
ns
1
–
1
–
ns
1
–
1
–
ns
5
–
4
–
8
–
14
–
6
–
ns
4
–
ns
8
–
ns
16
–
ns
NOTES:
COMMERCIAL AND INDUSTRIAL
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
8
FEBRUARY 13, 2009