ST162552 查看數據表（PDF） - Exar Corporation
零件编号
产品描述 (功能)
比赛名单
ST162552 Datasheet PDF : 28 Pages
| |||
ST16C2552
ST16C2552 ACCESSIBLE REGISTERS A/B
A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
000
RHR
bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
000
THR
bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
001
IER
0
0
0
0 modem receive transmit receive
status line holding holding
interrupt status register register
interrupt
010
FCR
RCVR RCVR
0
trigger trigger
MSB) (LSB)
0
DMA XMIT RCVR FIFO
mode FIFO FIFO enable
select reset reset
010
ISR
0/
0/
0
FIFOs FIFOs
enabled enabled
0
int
int
int
int
priority priority priority status
bit-2 bit-1 bit-0
011
LCR
divisor
latch
enable
set
break
set
parity
even parity stop
parity enable bits
word
length
bit-1
word
length
bit-0
1 0 0 MCR
0
0
0
loop OP2* OP1* RTS* DTR*
back
101
LSR
0/
FIFO
error
trans.
empty
trans. break framing
holding interrupt error
empty
parity
error
overrun receive
error data
ready
1 1 0 MSR
CD
RI
DSR CTS delta delta delta delta
CD*
RI* DSR* CTS*
111
SPR
bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
000
DLL
bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 DLM bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
0 1 0 AFR
0
0
0
0
0
MF* MF*
SP
sel-1 sel-0 write
These registers are accessible only when LCR bit-7 is set to “1”.
3-140
Share Link: 