STK12C68-C45 查看數據表（PDF） - Cypress Semiconductor
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STK12C68-C45 Datasheet PDF : 20 Pages
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STK12C68
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Parameter
Alt
tACE
tRC [7]
tAA [8]
tDOE
tOHA [8]
tLZCE [9]
tHZCE [9]
tLZOE [9]
tHZOE [9]
tPU [6]
tPD [6]
tELQV
tAVAV, tELEH
tAVQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
Switching Waveforms
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25 ns
Min Max
25
25
25
10
5
5
10
0
10
0
25
35 ns
Min Max
35
35
35
15
5
5
10
0
10
0
35
Figure 7. SRAM Read Cycle 1: Address Controlled [7, 8]
45 ns
Min Max
45
45
45
20
5
5
12
0
12
0
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W5&
$''5(66
W$$
W2+$
'4 '$7$287
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Figure 8. SRAM Read Cycle 2: CE and OE Controlled [7]
$''5(66
&(
2(
'4 '$7$287
W5&
W/=&(
W$&(
W'2(
W/=2(
W3'
W+=&(
W+=2(
'$7$9$/,'
W38
,&&
67$1'%<
Notes
7. WE and HSB must be High during SRAM Read cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
$&7,9(
Document Number: 001-51027 Rev. **
Page 9 of 20
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