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CMX673E3 查看數據表(PDF) - CML Microsystems Plc

零件编号
产品描述 (功能)
比赛名单
CMX673E3
CML
CML Microsystems Plc CML
CMX673E3 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1.6 Application Notes
1.6.1 General
On power-up, it will take 80ms to initialise the internal state, this delay should be accounted for
before the DETECT output is valid.
XTAL/CLOCK
1
C2
8
X1
R5
XTALN 2
7
VREF
R3
CMX673P1
R2
ENABLE
3
6
DETECT
4
_
5
SIGIN
+
R1
C3
R4
C4
Figure 3 A typical Telephone Line Circuit Application
R1 470k
R2 470k
R3 240k
R4 470k
R5 160k
C3 0.01µF 250V
C4 0.01µF 250V
Phone
Line
Note: 1. Resistors ±1%, Capacitors ±20% unless otherwise stated.
2. A low offset opamp is needed.
An alternative set of component values can be used:
R1 499k
R2 499k
R3 54.9k
R4 499k
R5 49.9k
C3 0.001µF 300V
C4 0.001µF 300V
Note: 3. Resistors ±1%, Capacitors ±2% unless otherwise stated.
4. A higher value of C3 and C4 will reduce the level sensitivity tolerance at around -38dBm.
© 2001 Consumer Microcircuits Limited
8
D/673/5

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