CXD3029R 查看數據表（PDF） - Sony Semiconductor
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CXD3029R Datasheet PDF : 201 Pages
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CXD3029R
Pin Description
Power Pin
supply No.
Symbol
I/O Value
Description
1 XRAS O 1, 0 DRAM row address strobe signal.
2 XWE O 1, 0 DRAM data input enable signal.
3 D1
I/O 1, 0 DRAM data bus 1.
4 D0
I/O 1, 0 DRAM data bus 0.
5 D3
I/O 1, 0 DRAM data bus 3.
6 D2
I/O 1, 0 DRAM data bus 2.
7 TEST1 O
Test pin. Do not connect.
8 TEST2 O
Test pin. Do not connect.
9 XCAS
2-3V
I/F 10 WFCK
11 A9
O 1, 0 DRAM column address strobe signal.
O 1, 0 WFCK output. XOE is output by switching with the command.
O 1, 0 DRAM address 9.
12 A8
O 1, 0 DRAM address 8.
13 A7
O 1, 0 DRAM address 7.
14 DVSS — — DRAM interface GND.
15 A6
O 1, 0 DRAM address 6.
16 A5
O 1, 0 DRAM address 5.
17 A4
O 1, 0 DRAM address 4.
18 XRDE
I/O 1, 0
DRAM readout enable signal input. XRDE monitor is output by switching
with the command.
19 VDD0 — — Digital power supply.
20 CLOK I
Serial data transfer clock input from CPU. SQSO and SENS readout
clocks are output by switching with the command.
21 DATA I
Serial data input from CPU.
22 SENS O 1, Z, 0 SENS output to CPU. SQSO data is output by switching with the command.
23 XLAT I
Latch input from CPU. The serial data is latched at the falling edge. XLAT
which is low for 6µs or more is enabled.
24 XSOE I
CPU serial data output enable signal.
Digital 25 SYSM I
Mute input. Muted when high.
26 WDCK O 1, 0 Word clock output f = 2Fs. GRSCOR is output by switching with the command.
27 SCOR
O
1, 0
High output when the subcode sync is detected. SCOR, which is
interpolated in the IC, is output by switching with the command.
28 XRST I
System reset. Reset when low.
29 PWMI I
Spindle motor external control input.
30 XQOK I/O 1, 0 Subcode Q OK input. XQOK monitor is output by switching with the command.
31
XWRE
I/O 1, 0
DRAM write enable signal input. XWRE monitor is output by switching with
the command.
–4–
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