TC35273 查看數據表（PDF） - Toshiba

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TC35273

TOSHIBA MPEG-4 Audiovisual LSI

Toshiba 

Preliminary

MPEG-4 Audiovisual Codec LSI

TC35273

ADIMCLK

TMCKW

ADSCLK

TSCKD

TSCKW

ADSDI

ADLRCLK

ADSDO

TSDIS

TSDIH

TLCKDH

TLCKDH

TSDOD

Fig. 15 Audio ADC&DAC Interface (Master clock input mode).

Table 16 Audio ADC&DAC Interface Timing (Master clock input mode).

Parameter

TMCKW

TSCKW

TSDIS

TSDIH

TLCKD

TSDOD

Description

Cycle time of ADIMCLK.

Duty ratio of ADIMCLK.

Cycle time of ADSCLK.

Delay time from ADIMCLK to ADSCLK.

Setup time of ADSDI.

Hold time of ADSDI.

Delay time from ADSCLK to ADLRLCK.

Delay time from ADSCLK from ADSDO.

Min Max

80

50±10

TMCKW*8

*3 TSYSCLK

*1 TSYSCLK

*4 TSYSCLK

*1 TSYSCLK

*6 TSYSCLK

Unit

ns

%

ns

ns

ns

ns

ns

ns

TOSHIBA Confidential

20/23

Version 0.90

2000-4-27

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