E-TDA7437N 查看數據表（PDF） - STMicroelectronics
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E-TDA7437N Datasheet PDF : 34 Pages
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TDA7437N
3
I2C bus interface
I2C bus interface
Data transmission from the microprocessor to the TDA7437N, and vice versa, takes place
through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pull-
up resistors to positive supply voltage must be externally connected).
3.1
Data validity
As shown in Figure 4, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
3.2
Start and stop conditions
As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP conditions must be sent before each START condition.
3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 6). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been
addressed has to generate an acknowledgment after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the
master transmitter can generate the STOP information in order to abort the transfer.
3.5
Transmission without acknowledgment
To avoid detection of the acknowledge clock pulse of the audioprocessor, the microprocessor can
use a simpler transmission: it simply waits one clock pulse, and sends the new data. This is less
protected from any errors and will decrease the immunity to noise.
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