TDA8706A 查看數據表（PDF） - Philips Electronics
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TDA8706A Datasheet PDF : 20 Pages
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Philips Semiconductors
6-bit analog-to-digital converter
with multiplexer and clamp
Product specification
TDA8706A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Timing (fclk = 40 MHz; CL = 20 pF); Tamb = 25 °C; see Fig.3
OUTPUT DATA; note 3
tds
sampling delay time
th
output hold time
td
output delay time
VDDO = 4.75 V
VDDO = 3.15 V
VDDO = 2.70 V
−
−
7
ns
5
−
−
ns
−
12
15
ns
−
17
20
ns
−
18
21
ns
SELECT INPUT SIGNALS SR, SG, SB AND CLP
tsu
set-up time SR, SG and SB with no overlap; see Fig.3 10
−
−
ns
with overlap
see Fig.4
ns
tr
rise time SR, SG and SB 10% to 90%
tf
fall time SR, SG and SB
90% to 10%
tover
R, G and B (active) overlap see Fig.4
time with respect to select
signals SR, SG and SB
4
6
4
6
0
−
−
ns
−
ns
−
ns
tCLPP
tMH
clamp pulse time
multiplexer hold time
SR, SG and SB
CCLP = 10 nF
−
3
9
−
−
µs
−
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
3. Output data acquisition: the output data is available after the maximum delay time of td.
1996 Jul 30
8
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