SM8703 查看數據表（PDF） - Nippon Precision Circuits

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SM8703

Clock Generator for MPEG2 System

Nippon Precision Circuits  

SM8703AV

Table 2. Mode resister function

Bit

D9

D8

D7

D6

D5

D4

D3/D2/D1/D0

Name

RSV

CE5

CE4

CE3

CE2

CE1

RSV

Function

Must be "LOW"

MO1, MO2 output enable/disable

SO5 output enable/disable

SO3, SO4 output enable/disable

SO2 output enable/disable

SO1 output enable/disable

Must be "LOW"

Table 3. Clock output control settings(CE5 to 1)

CE5 to CE1

LOW

HIGH

Clock output

Disable (Output fixed as "LOW")

Enable (Default)

Note

Output frequency changes according to the MDT pin condition, as MDT and FSEL pin (Sampling frequency

select signal input) are common. Refer to the section “Settling Time (when the sampling frequency is changed)”.

MCK

FSEL/MDT

MLEN

SO2 to 5

Stable

MREG (16bit data)

Unstable

Figure 5. Serial transfer timing

ts

Stable

NIPPON PRECISION CIRCUITS—9

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