SM8702AM
Operating Mode Summary
The state of the various external inputs and outputs in the operating modes is indicated in the following table.
MODE
SDRAM11/
CPU_STOP#
SDRAM10/
PCI_STOP#
CPUCLK[0:1]
PCICLK[0:4]
P C I C L K _ F,
24MHz/48MHz,
SDRAM[0:13]
Crystal
oscillator
VCO
(internal
signal)
Notes1
MODE = HIGH
(desktop
mode)
Enabled
(SDRAM output)
Enabled
(SDRAM output)
Enabled
Enabled
Enabled
Desktop mode.
Enabled Enabled Pins 17 and 18
function as outputs.
HIGH
HIGH
(CPU_STOP#input) (PCI_STOP# input)
HIGH
LOW
MODE = LOW (CPU_STOP#input) (PCI_STOP# input)
(mobile mode)
LOW
HIGH
(CPU_STOP#input) (PCI_STOP# input)
LOW
LOW
(CPU_STOP#input) (PCI_STOP# input)
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Mobile mode.
Pins 17 and 18
Enabled function as inputs.
Pin 17 =
Enabled CPU_STOP#
Pin 18 =
PCI_STOP#
Enabled
1. Enabled = output functions active. Disabled = LOW -level output.
CPU Clock Stop Function
In mobile mode, selected using MODE (pin 7), the CPUCLK[0:1] clock outputs can be stopped by external pin
control. The asynchronous stop signal input on CPU_STOP# is sampled internally on the rising edge of the
PCI free-running output clock (PCICLK_F).
When CPU_STOP# goes LOW, the CPU clock outputs (CPUCLK) stop after a delay of 2 to 4 clock cycles.
When CPU_STOP# goes HIGH, the CPU clock outputs start after a delay of 2 to 4 clock cycles. The actual
start and stop delay varies with the output frequency up to a maximum of 4 CPU clock cycles.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK_F
(free-running)
CPU_STOP#
PCI_STOP#
(All "H")
CPUCLK
(external)
NIPPON PRECISION CIRCUITS—12