HI5810 查看數據表（PDF） - Intersil

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产品描述 (功能)

比赛名单

HI5810

CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold

Intersil 

HI5810

Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 1.5MHz,

Unless Otherwise Specified (Continued)

25oC

-40oC TO 85oC

PARAMETER

Input Current, Static

TEST CONDITIONS

Conversion Stopped

MIN TYP MAX MIN

-

±0.6 ±10

-

MAX

±10

UNITS

µA

Input Bandwidth -3dB

-

1

-

-

-

MHz

Reference Input Current

-

160

-

-

-

µA

Input Series Resistance, RS

Input Capacitance, CSAMPLE

Input Capacitance, CHOLD

DIGITAL INPUTS OEL, OEM, STRT

In Series with Input CSAMPLE

During Sample State

During Hold State

-

420

-

-

-

380

-

-

-

20

-

-

-

Ω

-

pF

-

pF

High-Level Input Voltage, VIH

Low-Level Input Voltage, VIL

Input Leakage Current, IIL

Input Capacitance, CIN

DIGITAL OUTPUTS

Except CLK, VIN = 0V, 5V

2.4

-

-

2.4

-

V

-

-

0.8

-

0.8

V

-

-

±10

-

±10

µA

-

10

-

-

-

pF

High-Level Output Voltage, VOH

Low-Level Output Voltage, VOL

Three-State Leakage, IOZ

Output Capacitance, COUT

CLOCK

ISOURCE = -400µA

ISINK = 1.6mA

Except DRDY, VOUT = 0V, 5V

Except DRDY

4.6

-

-

4.6

-

V

-

-

0.4

-

0.4

V

-

-

±10

-

±10

µA

-

20

-

-

-

pF

High-Level Output Voltage, VOH

Low-Level Output Voltage, VOL

Input Current

TIMING

ISOURCE = -100µA (Note 2)

ISINK = 100µA (Note 2)

CLK Only, VIN = 0V, 5V

4

-

-

4

-

-

1

-

-

-

±5

-

-

V

1

V

±5

mA

Conversion Time (tCONV + tACQ)

(Includes Acquisition Time)

10

-

-

10

-

µs

Clock Frequency

Internal Clock, (CLK = Open)

200 300 400 150

500

kHz

External CLK (Note 2)

0.05

-

2.0

-

-

MHz

Clock Pulse Width, tLOW, tHIGH

Aperture Delay, tDAPR

Clock to Data Ready Delay, tD1DRDY

Clock to Data Ready Delay, tD2DRDY

Start Removal Time, tRSTRT

Start Setup Time, tSUSTRT

Start Pulse Width, tWSTRT

Start to Data Ready Delay, tD3 DRDY

Clock Delay from Start, tDSTRT

Output Enable Delay, tEN

Output Disabled Delay, tDIS

POWER SUPPLY CHARACTERISTICS

External CLK (Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

100

-

-

100

-

ns

-

35

50

-

70

ns

-

105 150

-

180

ns

-

100 160

-

195

ns

75

30

-

75

-

ns

85

60

-

100

-

ns

10

4

-

15

-

ns

-

65 105

-

120

ns

-

60

-

-

-

ns

-

20

30

-

50

ns

-

80

95

-

120

ns

Supply Current, IDD + IAA

-

2.6

8

-

8.5

mA

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

6-1780

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