XRD6414AIQ 查看數據表（PDF） - Exar Corporation

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XRD6414AIQ

CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter with 4:1 Input Analog Multiplexer

Exar Corporation 

XRD6414

ELECTRICAL CHARACTERISTICS (CONT’D)

Symbol

Parameter

Digital Inputs

VIH

Digital Input High Voltage

VIL

Digital Input Low Voltage

IIN

DC Leakage Currents6

CLK, OE, PD, A0, A1

Input Capacitance

Digital Outputs

VOH

VOL

IOZ

tDL

tDEN

tDHZ

Output High Voltage

Output Low Voltage

High-Z Leakage

Data Valid Delay2

Data Enable Delay

Data High-Z Delay

Pipeline Delay (Latency)

Power Supplies

IDD(PD) Power Down (IDD)

AVDD

DVDD

IDD

Operating Voltage7,8

Logic Power Supply9

Supply Current (IDD)

Min. Typ. Max. Unit

Conditions

3.5

V

1.5

V

5

mA Between AGND and AVDD

5

pF

4.5

V

0.4

V

–10

10

mA OE = high, or PD = high

10

12

14

ns

10

12

14

ns

7

8

9

ns

3

cycles Time delay between CLK and data

output

0.3

0.5

mA PD = high, excluding current

through reference ladder

4.5

5.0

5.5

V

2.7

5.5

V

24

32

mA PD = low

Notes

1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the

ideal code width (VREF/1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to

any transition voltage. Accuracy is a function of the sampling rate (FS).

2 Specified values guarantee functionality. Refer to other parameters for accuracy.

3 Guaranteed. Not tested.

4 –1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy

within the specified bandwidth.

5 See VIN equivalent circuit. Switched capacitor analog input requires driver with low output resistance.

6 All inputs have diodes to AVDD and AGND. Input DC currents will not exceed specified limits for any input voltage between AGND

and AVDD.

7 The GND pins are connected through the silicon substrate. Connect all GND pins together at the package and to the analog

ground plane. DGND and GND are connected through junction diodes. See logic output interface section.

8 The VDD pins should be tied together at the package.

9 See logic output interface section.

Specifications are subject to change without notice

Rev. 1.00

5

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