MP8775AQ 查看數據表（PDF） - Exar Corporation
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MP8775AQ Datasheet PDF : 8 Pages
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MP8775
Analog
Input
DNL LSB
Output
Codes
Code Width (N) = V(N+1) -- V(N)
LSB = [ VRT -- VRB ] / 256
DNL(N) = [ V(N+1) -- V(N) ] -- LSB
V(N+1)
V(N)
N+1
N
N--1
Figure 2. DNL Measurement
CLK
CLK
5pF
AVDD
VIN
AGND
VRT + VRB
2
CLK
1.5pF
6 pF
CLK
CLK
5pF
VIN [N--2]
CLK
1.5pF
Output
Codes
7
Real Transfer Line
6
5
INL
4
3
2
1
LSB
Best Fit Line
EFS
Ideal Transfer Line
EZS
Analog Input (Volt)
Figure 3. INL Error Calculation
+5 V
Analog
Input
0.1mF
0.1mF
50W
10mF
VIN
VDD DB7
DB6
VRTS
DB5
DB4
VRT
DB3
MP8775 DB2
VRB
VRBS
DB1
DB0
0.1mF
Digital
Outputs
CLK
GND
Clock
Figure 4. Equivalent Input Circuit
Figure 5. Typical Circuit Connections
APPLICATION NOTES
Signals should not exceed AVDD +0.5V or go below AGND
--0.5V or DVDD +0.5 V or DGND --0.5 V. All pins have internal
protection diodes that will protect them from short transients
(<100ms) outside the supply range.
AGND and DGND pins are connected internally through the
P-- substrate. DC voltage differences between these pins will
cause undesirable internal substrate currents.
The power supply (AVDD) and reference voltage (VRT & VRB)
pins should be decoupled with 0.1mF and 10mF capacitors to
AGND, placed as close to the chip as possible.
The digital outputs should not drive long wires or buses. The
capacitive coupling and reflections will contribute noise to the
conversion.
It is possible for the data valid delay (tDL) to be equal to or
greater than the high pulse width of the sampling clock (tPWH),
See Figure 1. This can cause timing related errors. For sample
rates above 14 MSPS use only the rising edge of the sample
clock (CLK) to latch data from the MP8775 to other parts of the
system.
The reference can be biased internally by shorting VRT to
VRTS and VRB to VRBS. This will generate 0.6 V at VRB and 2.6 V
at VRT (see Figure 5.).
If the internal reference pins VRTS and/or VRBS are not used
they should be left unconnected.
Rev. 3.01
5
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