IDT723613L30PQF 查看數據表（PDF） - Integrated Device Technology

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IDT723613L30PQF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

CLKB cycle. The logic diagram in Figure 2 shows the

previous bus-size selection is preserved when the mail

registers are accessed from port B. A port B bus-size is

implemented on each rising CLKB edge according to the

states of SIZ0_Q, SIZ1_Q, and BE_Q.

PARITY CHECKING

The port A data inputs (A0-A35) and port B data inputs (B0-

B35) each have four parity trees to check the parity of

incoming (or outgoing) data. A parity failure on one or more

bytes of the port A data bus is reported by a low level on the

port A parity error flag (PEFA). A parity failure on one or more

bytes of the port B data inputs that are valid for the bus-size

implementation is reported by a low level on the port B parity

error flag (PEFB). Odd or even parity checking can be se-

lected, and the parity error flags can be ignored if this feature

is not desired.

Parity status is checked on each input bus according to the

level of the odd/even parity (ODD/EVEN) select input. A parity

error on one or more valid bytes of a port is reported by a LOW

level on the corresponding port-parity-error flag (PEFA, PEFB)

output. Port A bytes are arranged as A0-A8, A9-A17, A18-

A26, and A27-A35, and port B bytes are arranged as B0-B8,

B9-B17, B18-B26, and B27-B35, and its valid bytes are those

used in a port B bus size implementation. When odd/even

parity is selected, a port-parity-error flag (PEFA, PEFB) is LOW

if any byte on the port has an odd/even number of LOW levels

applied to its bits.

The four parity trees used to check the A0-A35 inputs are

shared by the mail2 register when parity generation is se-

lected for port-A reads (PGA = HIGH). When a port A read

from the mail2 register with parity generation is selected with

CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA

HIGH, the port A parity error flag (PEFA) is held HIGH

regardless of the levels applied to the A0-A35 inputs. Like-

wise, the parity trees used to check the B0-B35 inputs are

shared by the mail1 register when parity generation is se-

lected for port B reads (PGB = HIGH). When a port B read from

the mail1 register with parity generation is selected with CSB

LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH, and

PGB HIGH, the port B parity error flag (PEFB) is held HIGH

regardless of the levels applied to the B0-B35 inputs.

PARITY GENERATION

A HIGH level on the port A parity generate select (PGA) or

port B generate select (PGB) enables the IDT723613 to

generate parity bits for port reads from a FIFO or mailbox

register. Port A bytes are arranged as A0-A8, A9-A17, A18-

A26, and A27-A35, with the most significant bit of each byte

used as the parity bit. Port B bytes are arranged as B0-B8, B9-

B17, B18-B26, and B27-B35, with the most significant bit of

each byte used as the parity bit. A write to a FIFO or mail

register stores the levels applied to all nine inputs of a byte

regardless of the state of the parity generate select (PGA,

PGB) inputs. When data is read from a port with parity

generation selected, the lower eight bits of each byte are used

to generate a parity bit according to the level on the ODD/

EVEN select. The generated parity bits are substituted for the

levels originally written to the most significant bits of each byte

as the word is read to the data outputs.

Parity bits for FIFO data are generated after the data is

read from SRAM and before the data is written to the output

register. Therefore, the port A parity generate select (PGA)

and odd/even parity select (ODD/EVEN) have setup and hold

time constraints to the port A clock (CLKA) and the port B

parity generate select (PGB) and ODD/EVEN select have

setup and hold time constraints to the port B clock (CLKB).

These timing constraints only apply for a rising clock edge

used to read a new long word to the FIFO output register.

The circuit used to generate parity for the mail1 data is

shared by the port B bus (B0-B35) to check parity and the circuit

used to generate parity for the mail2 data is shared by the port

A bus (A0-A35) to check parity. The shared parity trees of a port

are used to generate parity bits for the data in a mail register

when the port chip select (CSA, CSB) is LOW, enable (ENA,

ENB) is HIGH, and write/read select (W/RA, W/RB) input is

LOW, the mail register is selected (MBA HIGH for port A; both

SIZ0 and SIZ1 are HIGH for port B), and port parity generate

select (PGA, PGB) is HIGH. Generating parity for mail register

data does not change the contents of the register.

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