IDT72141 查看數據表（PDF） - Integrated Device Technology

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IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9

Integrated Device Technology 

IDT72131, IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9

tWC

W

D0–8

t WPW

tDS

Figure 2. Write Operation

COMMERCIAL TEMPERATURE RANGES

tWR

tDH

2751 drw 05

SOCP

SOX

SO(1)

SO (2)

t SOCW

1/f SOCP

0

t SOX

t SOHZ

t SOLZ

t SOPD

1

t SOCW

n–1

Figure 3. Read Operation

NOTES:

1. This timing applies to the Active Device in Width Expansion Mode.

2. This timing applies to Single Device Mode at Empty Boundary (EF = LOW) and the Next Active Device in Width Expansion Mode.

2751 drw 06

SOCP

W

FF

LAST WRITE

IGNORED

WRITE

FIRST READ

0

1

n–1

ADDITIONAL

READS

0

1

n–1

FIRST WRITE

t WFF

t SOCFF

Figure 4. Full Flag from Last Write to First Read

2751 drw 07

5.34

6

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