IDT72131L50P 查看數據表（PDF） - Integrated Device Technology

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IDT72131L50P

CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9

Integrated Device Technology 

IDT72131, IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9

COMMERCIAL TEMPERATURE RANGES

W

SOCP

EF

SO

LAST READ

NO READ

FIRST WRITE

ADDITIONAL

WRITES

FIRST READ

0

1

n–1

(1)

tSOCEF

t SOPD

VALID

t WEF

0

1

n–1

VALID

NOTE:

1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.

Figure 5. Empty Flag from Last Read to First Write

2751 drw 08

DATA IN

W

EF

SOCP

(1)

SO

t WEF

t REFSO

t SOCEF

0

1

t SOLZ

n–1

t SOPD

NOTE:

1. SOCP should not be clocked until EF goes HIGH.

Figure 6. Empty Boundary Condition Timing

2751 drw 09

5.34

7

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