TMC2193KJC 查看數據表（PDF） - Fairchild Semiconductor
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TMC2193KJC Datasheet PDF : 72 Pages
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TMC2193
Pin Assignments
100
1
81
80
30
31
51
50
65-6294-14
PRODUCT SPECIFICATION
Pin Function Pin Function Pin Function Pin Function
1 VDDA
31 PD19
51 PD1
81 FLD2
2 DAC4
32 PD18
52 PD0
82 FLD1
3 CBYP4 33 PD17
53 DGND
83 FLD0
4 AGND
34 PD16
54 VDD
84 CVBS9
5 DAC3
35 PD15
55 VSIN
85 CVBS8
6 CBYP3 36 PD14
56 HSIN
86 CVBS7
7 VDDA
37 PD13
57 DCVEN 87 CVBS6
8
RREF3
38 PD12
58 SER
88 CVBS5
9 AGND
39 VDD
59 CSVSCL 89 CVBS4
10 DAC2
40 DGND
60 R/WVSDA 90 CVBS3
11 CBYP2 41 PD11
61 A1/SA1 91 CVBS2
12 VDDA
42 PD10
62 A0/SA0 92 CVBS1
13 RREF2
43 PD9
63 D7
93 CVBS0
14 AGND
44 PD8
64 D6
94 RESET
15 DAC1
45 PD7
65 D5
95 PXCK
16 CBYP1 46 PD6
66 D4
96 VDD
17 VDDA
47 PD5
67 D3
97 DGND
18 RREF1
48 PD4
68 D2
98 VREF
19 REFDAC 49 PD3
69 D1
99 RREF4
20 KEY
50 PD2
70 D0
100 AGND
21 OL4
71 DGND
22 OL3
72 VDD
23 OL2
73 PDC
24 OL1
74 HSOUT
25 OL0
75 VSOUT
26 DGND
76 LINE4
27 PD23
77 LINE3
28 PD22
78 LINE2
29 PD21
79 LINE1
30 PD20
80 LINE0
Pin Definitions
Pin Name
Pin Number
Value Description
CLOCK, SYNC, & CONTROL INPUTS (6 pins)
DCVEN
57
TTL
Digital CVBS Output Enable. When DCVEN is LOW, the
Comp2 output prior to the D/A is routed to D7-0, FLD2-1
providing a digital composite output. When DCVEN is HIGH,
D7-0 and FLD2-1 operate in their normal mode.
HSIN
56
TTL
Horizontal Sync Input. When operating in slave, Genlock, or
DRS-Lock the TMC2193 will start a new horizontal line with
each falling edge of HSIN.
KEY
20
TTL
Hard Key selection. When the control register bit HKEN is set
HIGH and the hardware KEY pin is high, the video data
considered to be the foreground. is routed to the COMP2
output. This control signal is data aligned so that the pixel that is
present on the PD port when KEY signal is latched is at the
midpoint of the key transition. When HKEN is LOW, Key is
ignored.
4
REV. 1.0 3/26/03
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