TMC2193 查看數據表（PDF） - Fairchild Semiconductor

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TMC2193

10 Bit Encoder

Fairchild Semiconductor 

PRODUCT SPECIFICATION

TMC2193

Functional Description

Input Formats

Control Registers for this section

Address

0x05

0x05

0x06

Bit(s)

7

6-4

0

Name

D1OFF

INMODE

TSOUT

The TMC2193 supports both RGB and YCBCR component

sources on the pixel data port. For RGB sources the

TMC2193 will accept a 24 bit RGB source with a sample

rate of 4:4:4. YCBCR input sources are supported in 10 bit

4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2

cases the color difference components are linearly interpo-

lated to 4:4:4 internally.

Demuxing of multiplexed data streams depends on which

synchronization mode the encoder is operating in. For slave

and genlock modes the falling edge of HSIN must be LOW

prior to the CB data in order to demux the data correctly. For

master mode synchronization the falling edge of HSOUT

must be LOW prior to the Y data in order to demux the data

correctly. Finally, in 656 mode the demuxing of the data

stream is determined by the TRS codes, the first sample after

the TRS is considered a CB sample of the CB Y CR YI

packet.

The control register D1OFF controls the formatting of the

incoming luminance data at the pixel data port. When

D1OFF is HIGH a blanking level of 6410 is subtracted from

the luminance and when D1OFF is LOW the incoming the

pixel data is passed through. The inversion of the MSB’s on

the CB and CR components is controlled by the INMODE

control register.

INMODE 23

x00

7

101

9

110

9

111

9

CB/BLUE

YCBCR

CBCR

CBCR

16 15 14

07

0

0

0

PD

CR/RED

987

07

109

109

Figure 1. Input Formats

Y/GREEN

Y

Y

0

0

2

2

65-6294-02

1. INMODE = 000 or 100, PD[7:0] = Y/G, PD[23:16] = CB/B, PD[15:8] = CR/R

n = (SY+BR+BU+CBP+AV)*2

0

128

PXCK

PD[7:0]

(Y/G)n-1

(Y/G)n

PD[23:16]

(CB/B)n-1

(CB/B)n

PD[15:8] (CR/R)n-1

(CR/R)n

HSIN

HSOUT

(TSOUT = 1)

(Y/G)0

(CB/B)0

(CR/R)0

tSP

tDO

tDO

Figure 2. 24 Bit Input Format

x = (SY+BR+BU+CBP)*2

tS

tH

(Y/G)x

(Y/G)x+1

(Y/G)x+2

(CB/B)x

(CB/B)x+1

(CB/B)x+2

(CR/R)x

(CR/R)x+1

(CR/R)x+2

65-6294-03

2. INMODE = 101, PD[23:14] = YCBCR running at 27MHz.

The PD port is clocked at twice the pixel rate, with the data

organized as CB Y CR Y, with the cosited Y's following the

CB's. In its CCIR-656 time base mode, the demuxed CB, Y,

and CR data is synchronized to the SAV preamble. The first

data value, after the SAV preamble, is treated as a CB data

point in the multiplexed CB, Y, CR Y , D1 data stream.

Note: Figure 3, pixel numbering, reflects the SMPTE-125M

pixel numbering.

REV. 1.0 3/26/03

7

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