CDP68HC68W1E 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

比赛名单

CDP68HC68W1E

CMOS Serial Digital Pulse Width Modulator

Intersil 

CDP68HC68W1

SPI Interface Timing

PARAMETER

CDP68HC68W1, VDD = 5V ±10%, VSS = 0V, TA = -40oC to 85oC

Serial Clock Frequency

Cycle Time

Enable Lead Time

Enable Lag Time

Serial Clock (SCK) High Time

Serial Clock (SCK) Low Time

Data Setup Time

Data Hold Time

Fall Time (70% VDD to 20% VDD, CL = 200pF)

Rise Time (20% VDD to 70% VDD, CL = 200pF)

SYMBOL

MIN

fSCK

DC

tSCYC

480

tELD

240

tELG

-

tSH

190

tSL

190

tDSU

100

tDHD

100

tSCKF

-

tSCKR

-

MAX

UNITS

2.1

MHz

-

ns

-

ns

200

ns

-

ns

-

ns

-

ns

-

ns

100

ns

100

ns

CLK

PWM

tCYC

tCLKH

tR

tPWMO

tCLKL

FIGURE 1. PWM TIMING

tF

tPWMO

CS

(INPUT)

SCK

(INPUT)

DATA

(INPUT)

tSCYC

tELD

tSCKF

tELG

tSH

tSL

tSCKR

tDSU

MSB

tDHD

LSB

FIGURE 2. SERIAL PERIPHERAL INTERFACE TIMING

3

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