ADG714BRUZ(RevE) 查看數據表（PDF） - Analog Devices

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ADG714BRUZ
(Rev.:RevE)

CMOS, Low Voltage Serially Controlled, Octal SPST Switches

Analog Devices 

ADG714/ADG715

Data Sheet

Parameter

Cb

tSP3

Limit at TMIN, TMAX

400

50

Unit

pF max

ns max

Conditions/Comments

Capacitive load for each bus line

Pulse width of spike suppressed

1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

2 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 × VDD and 0.7 × VDD.

3 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

Timing Diagrams

SCLK

SYNC

DIN

DOUT

t10

t8

t4

DB7

t6

t5

t9

DB7*

DB6*

t1

t2

t3

t11

t7

DB0

DB2* DB1* DB0*

*DATA FROM PREVIOUS WRITE CYCLE

Figure 3. 3-Wire Serial Interface Timing Diagram

SDA

t9

t3

t10

t11

t4

SCL

t4

START

CONDITION

t2

t6

t5

t7

t1

REPEATED

START

CONDITION

Figure 4. 2-Wire Serial Interface Timing Diagram

t8

STOP

CONDITION

Rev. E | Page 8 of 21

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