CXL1502M 查看數據表（PDF） - Sony Semiconductor

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CXL1502M

CMOS-CCD Signal Processor

Sony Semiconductor 

CXL1502M

∗9 The internal clock component to the output signal during no-signal input and the leakage of that high

harmonic component are tested. The input block bias for VBIAS1 is tested at VID + 0.5V and VIC – 0.25V.

Test value [mVp-p]

∗10 C-CD is calculated in accordance with the following formula from the C-CD pin output voltage when a

200mVp-p, 4.437525MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and

from the C-CD pin output voltage when a 200mVp-p, 4.441431MHz sine wave is simultaneously fed to

same. The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is set to VID + 0.3V, VIY – 0.3V, VIC – 0.3V

and VIT – 0.3V, respectively.

C-CD pin output voltage (4.437525MHz)

C-CD = 20 log

[dB]

C-CD pin output voltage (4.441431MHz)

∗11 Y-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a

200mVp-p, 2.000011MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and

from the Y-YD pin output voltage when a 200mVp-p, 1.992198MHz sine wave is simultaneously fed to

same. The input block bias is set to the same conditions as in testing CCD.

Y-CD = 20 log Y-YD pin output voltage (1.992198MHz) [dB]

Y-YD pin output voltage (2.000011MHz)

CLOCK

fsc (4.433619MHz) sine wave

0.3Vp-p to 1.0Vp-p (0.4Vp-p Typ.)

–9–

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