HSP45314VI(2000) 查看數據表（PDF） - Intersil
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HSP45314VI Datasheet PDF : 14 Pages
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Timing Diagrams
HSP45314
WE
ADDR
DATA
WRITE
CLK
UPDATE
ANALOG OUT
tWS
tAS
A0
tAH
A1
tWH
A2
A3
A4
A5
DON’T CARE
W0
W1
tDS
tDH
W2
W3
W4
W5
6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD
DON’T CARE
DON’T CARE
DON’T CARE
tUS
tUD
tUL = 14 CLK RISING EDGES
OLD FREQ
NEW FREQ
FIGURE 2. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH)
WE
ADDR
DATA
WRITE
CLK
UPDATE
tWS
tAS tAH
A0
A1
tWH
A2
A3
A4
A5
DON’T CARE
W0
W1
tDS
tDH
W2
W3
W4
W5
t = 6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD
DON’T CARE
DON’T CARE
DON’T CARE
tUL= 11 CLK RISING EDGES
ANALOG OUT
PREVIOUS FREQ
PARTIAL UPDATES
ENTIRE NEW FREQ
FIGURE 3. PARALLEL-LOAD METHOD 2, UPDATE ACTIVE WHILE LOADING REGISTERS (RESET = HIGH)
3-11
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