AT80C32X2 查看數據表（PDF） - Atmel Corporation

零件编号

产品描述 (功能)

比赛名单

AT80C32X2

8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless

Atmel Corporation 

TS8xCx2X2

TS80C52X2 Serial I/O

Port

The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as

an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex

modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-

taneously and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (See Figure 6).

Figure 6. Framing Error Block Diagram

SM0/FE SM1 SM2 REN TB8 RB8 TI

RI SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD = 0)TS80C52X2

SMOD1SMOD0 -

POF GF1 GF0 PD IDL

To UART framing error control

PCON (87h)

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (See Table 9.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (See Figure 7. and Figure 8.).

Figure 7. UART Timings in Mode 1

RXD

RI

SMOD0=X

FE

SMOD0=1

D0 D1 D2 D3 D4 D5 D6 D7

Start

bit

Data byte

Stop

bit

17

4184I–8051–02/08

Share Link: