TSC102(2011) 查看數據表（PDF） - STMicroelectronics

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TSC102
(Rev.:2011)

High-side current sense amplifier plus signal conditioning amplifier

STMicroelectronics 

TSC102

Electrical characteristics

Table 9. Signal conditioning amplifier

Symbol

Parameter

Test conditions

Min.

Vicm Common mode voltage range

Tmin < Tamb < Tmax

0

VIO Input offset voltage

Va2 = 1 V

Tamb = 25° C

-40° C < Tamb < 150° C

ΔVIO Input offset voltage drift

Tmin < Tamb < Tmax

Iib Input bias current

Va2 = Va3 = VCC/2

Voh2

Output high-level saturation

voltage (Voh2 = VCC-Vout)

Va2 = 1 V Va3 = 0 V Iout = 1 mA

-40° C< Tamb < 125° C

Va2 = 0 V Va3 = 1 V

Vol2 Output low-level saturation voltage Iout = 1 mA

-40° C< Tamb < 125° C

Isc2 Short-circuit current

Out connected to VCC or Gnd 12

ΔVout/ΔIout Output stage load regulation

-10 mA < Iout < +10 mA

Va2 = 1 V

Iout sink or source current

CMR2

DC common mode rejection

Variation of VIO versus Vicm

Tmin < Tamb < Tmax

0 V<Va2<3 V

0 V<Va2<5 V

70

60

SVR2

Supply voltage rejection

Variation of VIO versus VCC

3.5 V<VCC<5.5 V

Va2 = 1 V

-40° C < Tamb < 125° C

85

GBP Gain bandwidth product

RL = 10 kΩ, Cload = 100 pF,

f = 100 kHz

PM Phase margin

SR Slew rate

RL = 10 kΩ, Cload = 100 pF

RL = 10 kΩ, Cload = 100 pF

Va2 = 0.5 V to 4.5 V

A3 connected to OUT (follower

configuration)

0.2

Slew rate measured from 10%

to 90% of Vout step

Typ.

5

10

85

75

30

95

80

105

1

65

0.4

Max.

Vcc

±3.5

±4.5

185

165

300

Unit

mV

µV/°C

pA

mV

mV

mA

µV/mA

dB

dB

MHz

deg

V/µs

Doc ID 16754 Rev 2

7/24

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