UPD16700 查看數據表（PDF） - NEC => Renesas Technology
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UPD16700 Datasheet PDF : 12 Pages
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µ PD16700
Switching Characteristics (TA = –20 to +75°C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = –10 V, VSS = 0 V)
Parameter
Cascade Output Delay Time
Driver Output Delay Time
Symbol
tPHL1
tPLH1
tPHL2
tPLH2
tPHL3
tPLH3
Condition
CL = 20 pF,
CLK → STVL (STVR)
CL = 300 pF, CLK → On
CL = 300 pF, OEn → On
MIN.
TYP.
MAX.
Unit
240
800
ns
240
800
ns
240
800
ns
240
800
ns
240
800
ns
240
800
ns
Output Rise Time
tTLH
CL = 300 pF
350
ns
Output Fall Time
Input Capacitance
tTHL
CI
TA = 25 °C
350
ns
6.0
15
pF
Timing Requirements (TA = –20 to +75°C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = –10 V, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock Pulse High Width
PWCLK(H)
500
ns
Clock Pulse Low Width
Enable Pulse Width
PWCLK(L)
PWOE
500
ns
1.0
µs
Data Setup Time
tSETUP STVR (STVL) ↑ → CLK ↑
200
ns
Data Hold Time
tHOLD CLK ↑ → STVR(STVL) ↓
200
ns
Caution Keep the time and fall time of the logic input to tr = tf = 20 ns (10 to 90% of the rated values).
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1. For details, refer
to Switching Characteristic Waveform.
Data Sheet S14085EJ3V0DS
7
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